Asynchronous LVDS Transceiver for Versal devices - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

The LVDS Transceiver block replaces the functionality provided by a Device Transceiver but only at 1.25Gbps line rate. The further details of this block are as discussed below.

Figure 1. Top-Level Hierarchy of Asynchronous LVDS Transceiver for Versal Devices

The Data Transmit logic is similar to that of UltraScale/UltraScale+ devices. The 8-bit parallel data from TX 10-bit to 8-bit gearbox, synchronous to 156.25Mhz clock is fed to the Advanced IO Wizard.

The Receiver path has been simplified as the Advanced IO Wizard sub-core detects the data sampling point through it's CDR logic and provides 8-bit parallel data synchronous to a 312.5Mhz clock, qualified with data valid. RX Gearbox converts 8-bit parallel data from the wizard, to 10-bit comma aligned parallel data at 312.5Mhz, qualified with data valid.

Data is then passed through a clock correction buffer and the 10b/8b decoder block in the same way as it is done for UltraScale/UltraScale+ devices.