This section provides guidelines for creating synchronous SGMII designs using Zynq 7000 and 7 series device LVDS. Supported devices are shown in the following table. This mode enables direct connection to external PHY devices without the use of an FPGA transceiver. An example implementation is shown in the following figure.
| Family | Supported Devices |
|---|---|
| Zynq 7000 |
-2 speed grade or faster for XC7Z010/20 devices and -1 speed grade or faster for XC7Z030/45/100 devices |
| Virtex 7 |
-2 speed grade or faster for devices with HR Banks or -1 speed grade or faster for devices with HP banks |
| Kintex 7 |
-2 speed grade or faster for devices with HR Banks or -1 speed grade or faster for devices with HP banks |
| Artix 7, Spartan 7 | -2 speed grade or faster |
For information about the SGMII over LVDS example design see Synchronous SGMII over LVDS Example Design (Applicable for Non-Versal Devices).
A detailed understanding of 7 series FPGA Clocking Resources and SelectIO Resources is useful to understand the core operation. See the 7 Series FPGAs SelectIO Resources User Guide (UG471) and 7 Series FPGAs Clocking Resources User Guide (UG472).