serdes_1_to_10 - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
PG047
Release Date
2023-11-01
Version
16.2 English

This module adjusts input delays for the RX_BITSLICE in order to sample the data in the middle of the data eye. Two RX_BITSLICEs are fed with the serial data but phase shifted with respect to each other by 400 ps (one half bit period). One of the RX_BITSLICE is always kept at the boundary of serial data eye, ensuring that another RX_BITSLICE is sampling the data at the center of the data eye. This module changes the delays of the RX_BITSLICEs dynamically while selecting the valid data from the two RX_BITSLICES.

This module is also responsible for comma alignment and gives out comma-aligned data at the interface along with a data valid signal, synchronous to the 312.5 MHz local clock.

The following file describes the serdes_1_to_10 functionality:

<project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/

synth/lvds_transceiver/<component_name>_serdes_1_to_10.v