IODELAYs and ISERDES - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

This logic, along with eye monitor and PHY calibration, is used to convert incoming serial data into 6-bit parallel data. See IODELAYs and RDES in the 7 series FPGAs SelectIOResources User Guide (UG471) for more information on these primitives.