Asynchronous LVDS Clocking and Reset Logic (Applicable for non Versal devices) - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

The asynchronous LVDS solution is an implementation where an external clock is provided to the design. This clock can be asynchronous to the incoming data stream within the limits specified in the Ethernet specifications. This 625 MHz differential clock is fed to an IBUFDS and the output drives the input of two PLLs. When implementing synchronous SGMII interfaces using this solution, the reference clock is user-selectable.

A PLL is used to generate multiple clocks at 312.5,125 MHz along with the 625,1250 MHz tx_pll_clock and rx_pll_clock driven to TX_BITSLICE_CONTROL and RX_BITSLICE_CONTROL. The clocking and reset logic is included in a separate module <component_name>_clock_reset which is instantiated in the <component_name>_support module .

The core supports up to three instances of PCS/PMA lanes within a single BYTE_GROUP. The core can be extrapolated to the full bank using multiple instances (up to four for an I/O bank) of three lane core instances. However one differential pair of clocks is required to drive the PLLs in the bank. This limits the maximum number of Ethernet links in an I/O bank to 11. This is shown in the following figure.

Figure 1. Multi-Lane Asynchronous LVDS Core in a Full-Bank Design Ethernet 1000BASE-X PCS/PMA or SGMII Page-1 Sheet.1 Sheet.2 BitSlice BitSlice Sheet.3 and and Sheet.4 Logic Logic Sheet.5 Clocking Logic Clocking Logic Sheet.6 Sheet.7 Control Control Sheet.8 Sheet.9 Shared Logic Shared Logic Sheet.10 Sheet.11 Sheet.12 Sheet.14 Sheet.15 Logic Logic Sheet.17 Sheet.18 BitSlice BitSlice Sheet.19 and and Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 TX and RX BITSLICE and BITSLICE_CONTROL TX and RX BITSLICE and BITSLICE_CONTROL Sheet.26 Asynchronous LVDS Asynchronous LVDS Sheet.27 Asynchronous LVDS Asynchronous LVDS Sheet.28 Asynchronous LVDS Asynchronous LVDS Sheet.29 Ethernet IP Logic Ethernet IP Logic Sheet.30 Ethernet IP Logic Ethernet IP Logic Sheet.31 Ethernet IP Logic Ethernet IP Logic Sheet.32 Clocking Logic Clocking Logic Sheet.33 Reset Sequence Reset Sequence Sheet.34 Clock_reset Clock_reset Sheet.38 Lane 1 Lane 1 Sheet.39 Lane 2 Lane 2 Sheet.40 Lane 3 Lane 3 Sheet.41 BaseX_Byte BaseX_Byte Sheet.42 BitSlice BitSlice Sheet.43 and and Sheet.44 Logic Logic Sheet.45 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Asynchronous LVDS Asynchronous LVDS Sheet.52 Ethernet IP Logic Ethernet IP Logic Sheet.54 Lane 4 Lane 4 Sheet.55 TX and RX BITSLICE and BITSLICE_CONTROL TX and RX BITSLICE and BITSLICE_CONTROL Sheet.56 Sheet.57 Sheet.58 Sheet.59 Asynchronous LVDS Asynchronous LVDS Sheet.60 Ethernet IP Logic Ethernet IP Logic Sheet.62 Lane 5 Lane 5 Sheet.63 Sheet.64 Sheet.65 Sheet.66 Asynchronous LVDS Asynchronous LVDS Sheet.67 Ethernet IP Logic Ethernet IP Logic Sheet.69 Lane 6 Lane 6 Sheet.70 Sheet.71 Sheet.72 Sheet.73 Sheet.74 Sheet.77 Sheet.78 I/O Bank I/O Bank Sheet.80 Sheet.81 Standard Arrow.14 Standard Arrow.83 Standard Arrow.84 Standard Arrow.85 Standard Arrow.86 Standard Arrow.87 Standard Arrow.88 Standard Arrow.89 Sheet.79 X17631-081816 X17631-081816

Typical use of the asynchronous LVDS solution involves multiple instances of the LVDS solution with a single clocking block. One instance of the core is generated with the Include Shared Logic in Core option. This instance contains all the clocking and reset logic that can be shared. The remaining instances can be generated using the Include Shared Logic in Example Design option.

The reset logic contains the reset sequence required in native I/O mode. The reset sequence is used to calibrate the delays and provides the rx_bt_val value to the core logic. This value is used to calculate the number of taps required to maintain a relative difference of 400 ps between two RX_BITSLICEs.