SGMII Ports - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)
Document ID
PG047
Release Date
2023-11-01
Version
16.2 English

The following table describes the SGMII interface ports.

Table 1. SGMII Interface Ports
Signal Direction Description
sgmii_clk_en Output Clock for GMII transmit data
sgmii_clk_f Output Differential clock for GMII transmit data
sgmii_clk_r Output Differential clock for GMII transmit data
recclk_mmcm_reset Output

MMCM reset for MMCM generating rxuserclk, rxuserclk2, when RxGmiiClkSrc=RXOUTCLK.

This is output only when the clocking logic is a part of the example design and applicable only for 7 series devices with MMCM is used for clock multiplication.
sgmii_rx_clk_en Output Clock enable for GMII receive data when RxGmiiClkSrc=RXOUTCLK in SGMII mode.
sgmii_rx_clk_f Output Differential clock for GMII receive data when RxGmiiClkSrc=RXOUTCLK in SGMII mode.
sgmii_rx_clk_r Output Differential clock for GMII receive data when RxGmiiClkSrc=RXOUTCLK in SGMII mode.
speed_is_10_100 Input

Speed control for controlling operating speed of SGMII interface. Not applicable for 2.5G SGMII.

Valid Values: 0 for 1 Gbps

1 for 10/100 Mbps
speed_is_100 Input

Speed control for controlling operating speed of SGMII interface. Not applicable for 2.5G SGMII.

Valid Values: 0 for 1 Gbps and 10 Mbps

1 for 100 Mbps