Method 2: Alternative Using Both pma_rx_clk0 and pma_rx_clk1 - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English
Figure 1. Alternate TBI Receiver Logic – Kintex 7 Devices pma_rx_clk0 BUFIO IOB LOGIC IP AD rx_code_g roup[0] IB UF IP AD pma_rx_clk0 B UFR IOB LOGIC pma_rx_clk1 rx_code_g roup0[0] rx_code_g roup1[0] D Q1 pma_rx_clk0_b ufr (62.5 MHz) IODEL A Y D Q pma_rx_clk0 BUFIO IOB LOGIC IP AD B UFR pma_rx_clk1_b ufr (62.5 MHz) IDDR_CLK2 Q2 D Q C CB X12878 EncryptedRTL

This logic from Method 1 relies on pma_rx_clk0 and pma_rx_clk1 being exactly 180° out of phase with each other because the falling edge of pma_rx_clk0 is used in place of pma_rx_clk1. See the data sheet for the attached SerDes to verify that this is the case. If not, the logic of the previous shows an alternate implementation where both pma_rx_clk0 and pma_rx_clk1 are used as intended. Each bit of rx_code_group[9:0] must be routed to two separate device pads.

In this method, the logic used on pma_rx_clk0 in Figure 1 is duplicated for pma_rx_clk1. An IDDR_CLK2 primitive replaces the IDDR primitive; this contains two clock inputs as shown.