Integration of the TEMAC Core Using Sync SGMII over LVDS - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
PG047
Release Date
2023-11-01
Version
16.2 English

The following figure shows the connections and clock management logic required to interface the core (in Sync SGMII over LVDS) to the Zynq 7000 device PS ENET0/1. The 2.5G mode is not supported in this case. The following conditions apply to each connected the Zynq 7000 device PS ENET0/1 and SGMII port pair:

  • The SGMII Adaptation module, as provided in the example design for the core when generated to the SGMII standard, can be used to interface the two cores.
  • The MDIO port can be connected up to that of the Zynq 7000 device PS ENET0/1, allowing the MAC to access the embedded configuration and status registers of the 1G/2.5G Ethernet PCS/PMA or SGMII core.
  • clk125 is used as the 125 MHz reference clock for both cores, and the transmitter and receiver logic of theZynq 7000 device PS ENET0/1 now operate in the same clock domain. This is the clock derived by MMCM and IBUFDS from differential reference clock.