Important: The DRU must have at least two valid sampling
points per data bit, requiring 0.5 UI of opening. The settings of the FPGA add 0.125 UI
of requirement making a total opening requirement at the receiver of 0.625 UI.
Recommended: For Chip-to-Chip Copper Implementations, this
interface supports an SGMII link between the FPGA and an external PHY device across a
single PCB; keep the SGMII copper signal lengths to a minimum.