Case 1 - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

The following figure shows a simplified diagram of a common situation where the core, in SGMII mode, is interfaced to an external PHY device. A common oscillator source is used for both the FPGA and the external PHY.

Figure 1. SGMII Implementation Using Shared Clock Sources Ethernet 1000BASE-X PCS/PMA or SGMII Page-1 Sheet.1 FPGA FPGA Sheet.2 1G/2.5G Ethernet PCS/PMA or SGMII Core 1G/2.5G Ethernet PCS/PMA or SGMII Core Sheet.3 Transceiver Transceiver Sheet.4 RX Elastic Buffer RXElasticBuffer Sheet.5 10BASE-T 100BASE-T 1000BASE-T PHY 10BASE-T100BASE-T1000BASE-TPHY Sheet.6 RXP/RXN RXP/RXN Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 125 MHz -100 ppm 125 MHz -100 ppm Sheet.14 Twisted Copper Pair TwistedCopperPair Sheet.15 TXP/TXN TXP/TXN Sheet.16 SGMII Link SGMII Link Standard Arrow.17 Standard Arrow.8 Standard Arrow.9 Standard Arrow.10 Sheet.21 X12863 X12863 Sheet.22 Sheet.23 Sheet.24

If the PHY device sources the receiver SGMII stream synchronously from the shared oscillator (check PHY data sheet), the device-specific transceiver receives data at exactly the same rate as that used by the core. The receive elastic buffer neither empties nor fills, having the same frequency clock on either side.

In this situation, the receive elastic buffer does not under or overflow, and the elastic buffer implementation in the device-specific transceiver should be used to save logic resources.