Block Level - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

The block level is designed so that it can be instantiated directly into customer designs and performs the following functions:

  • Instantiates the core level HDL
  • Connects the physical-side interface of the core to device IOBs, creating an external TBI TBI, including IOB and DDR registers instances, where required
For SGMII/Dynamic Switching with a TBI the block level also has an SGMII Adaptation Module containing:
  • The clock management logic required to enable the SGMII example design to operate at 10 Mbps, 100 Mbps, and 1 Gbps.
  • GMII logic for both transmitter and receiver paths; the GMII style 8-bit interface is run at 125 MHz for 1 Gbps operation; 12.5 MHz for 100 Mbps operation; 1.25 MHz for 10 Mbps operation.

The block level HDL connects the TBI of the core to external IOBs (the most useful part of the example design) and should be instantiated in all customer designs that use the core.

The file location for the SGMII Adaptation Module is described in SGMII Adaptation Module. The SGMII adaptation module and component blocks are described in detail in Additional Client-Side SGMII Logic.