Register 0: Control Register - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)
Document ID
PG047
Release Date
2023-11-01
Version
16.2 English
Figure 1. MDIO Register 0: Control Register Ethernet 1000BASE-X PCS/PMA or SGMII Page-1 Sheet.1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 RESET RESET Sheet.11 LOOPBACK LOOPBACK Sheet.12 AUTO-NEG ENABLE AUTO-NEG ENABLE Sheet.13 RESTART AUTO-NEG RESTART AUTO-NEG Sheet.14 RESERVED RESERVED Sheet.15 POWER DOWN POWER DOWN Sheet.16 SPEED SPEED Sheet.17 SPEED SPEED Sheet.18 15 15 Sheet.19 14 14 Sheet.20 13 13 Sheet.21 12 12 Sheet.22 11 11 Sheet.23 10 10 Sheet.24 7 7 Sheet.25 6 6 Sheet.26 5 5 Sheet.27 0 0 Sheet.28 Reg 0 Reg 0 Sheet.29 Sheet.30 ISOLATE ISOLATE Sheet.31 Sheet.32 9 9 Sheet.33 Sheet.34 8 8 Sheet.35 DUPLEX MODE DUPLEX MODE Sheet.36 COLLISION TEST COLLISION TEST Sheet.37 Sheet.38 4 4 Sheet.39 UNIDIRECTIONAL ENABLE UNIDIRECTIONAL ENABLE Sheet.40 X12801 X12801

This register can also be programmed using the optional configuration interface.

Table 1. Register 0 – Control Register
Bits Name Description Attributes Default Value
0.15 Reset

1 = Core Reset

0 = Normal Operation

R/W

Self clearing

 0
0.14 Loopback

1 = Enable Loopback Mode

0 = Disable Loopback Mode

When used with a device-specific transceiver, the core is placed in internal loopback mode.

Note: Loopback is not supported by the core when RxGmiiClkSrc=RXOUTCLK.

In TBI mode, bit 1 is connected to the ewrap signal. When set to 1, indicates to the external PMA module to enter loopback mode. See Loopback.

 R/W 0
0.13 Speed Selection (LSB)

1000BASE-X/2500BASE-X :

Always returns a 0 for this bit. Together with bit 0.6, a speed selection of 1000 Mbps is identified.

In 2.5G mode this bit along with bit 0.6, indicates a speed selection of 2500 Mbps.

SGMII:

11 = Reserved

10 = 1 Gbps

01 = 100 Mbps

00 = 10 Mbps

Zynq 7000, Zynq MPSoC and Zynq RFSoc PS Gigabit Ethernet Controller mode, identifies with bit 0.13 of Control register specified in IEEE 802.3-2008.

1000BASE-X/2500BASE-X :

Returns 0

SGMII:

R/W in Zynq 7000, Zynq MPSoC and Zynq RFSoc PS Gigabit Ethernet Controller mode.

Returns 0 in any other mode

 0
0.12 Auto-Negotiation Enable

Using optional auto-negotiation:

1 = Enable Auto-Negotiation process

0 = Disable Auto-Negotiation process

Without optional auto-negotiation:

Bit is reserved

 R/W 1
0.11 Power Down

1 = Power down

0 = Normal operation

With the PMA option, when set to 1 the device-specific transceiver is placed in a low-power state. This bit requires a reset (see bit 0.15) to clear.

In TBI mode this register bit has no effect.

 R/W 0
0.10 Isolate

1000BASE-X/2500BASE-X :

1 = Electrically isolate PHY from GMII

SGMII:

Electrically isolate SGMII logic from GMII

0 = Normal operation

 R/W 1
0.9 Restart Auto- Negotiation

Using optional auto-negotiation:

1 = Restart auto-negotiation process

0 = Normal operation

Without optional auto-negotiation:

Bit is reserved

R/W

Self clearing

 0
0.8 Duplex Mode Always returns a 1 for this bit to signal Full-Duplex mode. Returns 1 1
0.7 Collision Test Always returns a 0 for this bit to disable COL test. Returns 0 0
0.6 Speed Selection (MSB)

1000BASE-X/2500BASE-X :

Always returns a 1 for this bit. Together with bit 0.13, a speed selection of 1000 Mbps is identified.

In 2.5G mode this bit, along with bit 0.13, indicates a speed selection of 2500Mbps.

SGMII:

11 = Reserved

10 = 1 Gbps

01 = 100 Mbps

00 = 10 Mbps

Zynq 7000, Zynq MPSoC and Zynq RFSoc PS Gigabit Ethernet Controller mode, identifies with bit 0.6 of Control register specified in IEEE 802.3-2008.

1000BASE-X/2500BASE-X :

Returns 1

SGMII:

R/W inZynq 7000 , Zynq MPSoC and Zynq RFSocPS Gigabit Ethernet Controller mode.

Returns 1 in any other mode

 1
0.5 Unidirectional Enable

Enable transmit regardless of whether a valid link has been established.

This feature is only possible if Auto-Negotiation Enable (bit 0.12) is disabled.

 R/W 0
0.4:0 Reserved Always return 0s, writes ignored. Returns 0s 00000