Clock Sharing Across Multiple Cores with Asynchronous LVDS Transceiver (Applicable for non Versal devices) - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

One instance of the core is generated with the Include Shared Logic in Core option. This instance contains all the clocking logic that can be shared. The remaining instances can be generated using the Include Shared Logic in Example Design option. The following figure shows sharing clock resources across three instantiations of the core. This can be extrapolated to a maximum of four instances within the same bank.

Figure 1. Clock Sharing Across Three Core Instantiations