Test Bench - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

This chapter contains information about the demonstration test bench provided in the AMD Vivado™ Design Suite.

The following figure shows the demonstration test bench for the core using the TBI, a device-specific transceiver or the LVDS transceiver. The demonstration test bench is a simple VHDL or Verilog program to exercise the example design and the core.

Figure 1. Demonstration Test Bench Demonstration Test Bench TBI/PMA/SGMII* Monitor (Serial to Parallel Conversion and 8B10B Decoding)* TBI/PMA/SGMII* Stimulus (8B10B Encoding and Parallel to Serial Conversion)* GMII Stimulus GMII Monitor GMII DUT Control and Data Structures Configuration Stimulus X12832 TBI/DeviceSpecificTransceiver/LVDSTransceiver* * Configuration-dependent

The top level test bench entity instantiates the example design for the core, which is the Device Under Test (DUT). A stimulus block is also instantiated and clocks, resets, and test bench semaphores are created. The following files describe the top level of the demonstration test bench:

<project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/ simulation/demo_tb.v[hd]

The stimulus block entity, instantiated from within the test bench top level, creates the Ethernet stimulus in the form of four Ethernet frames, which are injected into the GMII and PHY interfaces of the DUT. The output from the DUT is also monitored for errors. The following files describe the stimulus block of the demonstration test bench.

<project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/ simulation/stimulus_tb.v[hd]

Together, the top level test bench file and the stimulus block combine to provide the full test bench functionality, described in the sections that follow.