The following figure shows a typical application for the core, where the core is providing a GMII to SGMII bridge using a device-specific transceiver to provide the serial interface.
- The device-specific transceiver is connected to an external off-the-shelf Ethernet PHY device that also supports 1G or 2.5G SGMII. (This can be a tri-mode PHY providing 10BASE-T, 100BASE-T, and 1000BASE-T operation for 1G.)
- The core GMII interface is connected to an embedded Ethernet MAC, for example, the AMD Tri-Mode Ethernet MAC core (in supported devices) or Ethernet MAC (EMAC0 or EMAC1) present in the AMD Zynq™ 7000 SoC or PS or Gigabit Ethernet MAC (GEM0 or GEM1) present in Zynq AMD UltraScale+™ or AMD Versal™ CIPS. The core does not support 2500BASE-X and 2.5G SGMII when the core is generated to interface with the Ethernet MAC (EMAC0 or EMAC1) present in the AMD Zynq™ 7000 SoC or Gigabit Ethernet MAC present in Zynq AMD UltraScale+™ PS or AMD Versal™ CIPS.
Figure 1. Typical Application for GMII to SGMII Bridge Mode
