Asynchronous 1000BASE-X/SGMII over LVDS - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

This section provides the guidelines for creating asynchronous 1000BASE-X/SGMII interfaces using UltraScale/UltraScale+ device LVDS. This mode enables direct connection to external PHY devices without the use of an FPGA transceiver. 2.5G SGMII/2.5G BASE-X is unsupported for the LVDS physical interface.

Important: The Asynchronous 1000BASE-X/SGMII over LVDS implementation can fully support synchronous SGMII interfaces. This can be accomplished through the Clock Selection parameter in GUI.

In UltraScale devices, for the SGMII interface, an option is provided to choose between the Synchronous SGMII over LVDS solution that uses native components and the Asynchronous SGMII over LVDS solution that uses SelectIOtechnology using the parameter, EnableAsyncSGMII.

The synchronous SGMII over LVDS solution uses component mode I/Os such as ISERDES, OSERDES, IDELAY, ODELAY components whereas the asynchronous implementation uses native mode HSSIO components such as BITSLICE and BITSLICE_CONTROL.