SGMII/Dynamic Switching with TBI Example Design - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

The following figure shows an example design for the top level HDL for the core in SGMII (or dynamic switching) mode with the TBI. The 2.5G mode is not supported in this case.

Figure 1. Example Design HDL for the Core in SGMII Mode with TBI