The core can fully support SGMII using standard LVDS SelectIO technology logic
resources. This enables direct connection to external PHY devices without the use of an
FPGA transceiver. This implementation is shown in the following figure. The core does
not supports 2.5G SGMII modes for the LVDS physical interface. Synchronous LVDS mode is
not supported for AMD Versalâ„¢
devices.
Figure 1. Core Block Diagram with Standard SelectIO Technology Support for SGMII
Note: For UltraScale devices, clocking logic generates 125, 312.5, and 625 MHz
clocks respectively. Frequencies shown in the previous figure are applicable for
7 series devices.
As shown in the previous figure, the Hardware Description Language (HDL)
example design for this implementation provides additional logic to form the LVDS
transceiver. The LVDS transceiver block fully replaces the functionality otherwise
provided by an UltraScale or 7 series FPGA transceiver. This is only possible at a
serial line rate of 1.25 Gbps. The following subsections describe the design
requirements.