This module creates the
sgmii_clk_en
clock enable signal for use
throughout the SGMII adaptation module. Clock enabled frequencies are:- 125 MHz at an operating speed of 1 Gbps
- 12.5 MHz at an operating speed of 100 Mbps
- 1.25 MHz at an operating speed of 10 Mbps
The following figure shows the output clock enable signal for the Clock Generation module at 1 Gbps and 100 Mbps speeds.
Figure 1. Clock Generator Output Clocks and Clock Enable
The above figure also shows the formation of the sgmii_clk_r
and
sgmii_clk_f
signals. These are used only in the example design
delivered with the core, where they are routed to a device IOB DDR output register. This
provides SGMII clock forwarding at the correct frequency; these signal can be ignored
when connecting the core and SGMII Adaptation module to internal logic.