Simulation - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

A highly parameterizable transaction based test bench was used to test the core. Testing included the following:

  • Register Access
  • Loss of Synchronization
  • Auto-Negotiation and error handling
  • Frame Transmission and error handling
  • Frame Reception and error handling
  • Clock compensation in the elastic buffers

AMD UltraScale+™ , AMD UltraScale™ , AMD Zynq™ 7000, and 7 series device designs incorporating a device-specific transceiver require a Verilog LRM-IEEE 1364-2005 encryption-compliant simulator. For IP simulation, a mixed simulation license is required.