Core with the TBI - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
PG047
Release Date
2023-11-01
Version
16.2 English

There is no physical loopback path in the core. Placing the core into loopback has the effect of asserting logic 1 on the ewrap signal of the TBI (see TBI Ports). This instructs the attached PMA SerDes device to enter loopback mode as shown in the following figure.

Figure 1. Loopback Implementation Using the TBI Ethernet 1000BASE-X PCS/PMA or SGMII Page-1 Sheet.1 1000BASE-X PMA SERDES 1000BASE-X PMASERDES Sheet.2 Sheet.3 Sheet.4 1G/2.5G Ethernet PCS/PMA or SGMII Core 1G/2.5G Ethernet PCS/PMA or SGMII Core Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 TX TX Sheet.13 RX RX Sheet.14 TBI TBI Sheet.15 Sheet.16 Device Logic Device Logic Sheet.17 Loopback occurs in external SERDES Loopback occurs in external SERDES Sheet.18 X12799-031417 X12799-031417 Standard Arrow.19 Sheet.20 Standard Arrow.47 Standard Arrow.13 Standard Arrow.14 Standard Arrow.22