Receiver Logic - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
PG047
Release Date
2023-11-01
Version
16.2 English
Figure 1. Input TBI timing t SETUP t HOLD rx_code_ g roup[9:0] PMA_RX_CLK0 t SETUP t HOLD PMA_RX_CLK1 X12796

The previous figure shows the input timing for the TBI interface as defined in IEEE802.3-2008 clause 36.

Note: The important point is that the input TBI data bus, rx_code_group[9:0], is synchronous to two clock sources: pma_rx_clk0 and pma_rx_clk1. As defined by the standard, the TBI data should be sampled alternatively on the rising edge of pma_rx_clk0, then pma_rx_clk1. Minimum setup and hold constraints are specified and apply to both clock sources.

In the IEEE802.3-2008 specification, there is no exact requirement that pma_rx_clk0 and pma_rx_clk1 be exactly 180° out of phase with each other, so the safest approach is to use both pma_rx_clk0 and pma_rx_clk1 clocks as the specification intends. This is at the expense of clocking resources.

However, the data sheet for a particular external SerDes device that connects to the TBI might well specify that this is the case; that pma_rx_clk0 and pma_rx_clk1 are exactly 180° out of phase. If this is the case, the TBI receiver clock logic can be simplified by ignoring the pma_rx_clk1 clock altogether, and simply using both the rising and falling edges of pma_rx_clk0.

For this reason, the following sections describe two different alternatives methods for implementing the TBI receiver clock logic: one which uses both pma_rx_clk0 and pma_rx_clk1 clock, and a second which only uses pma_rx_clk0 (but both rising and falling edges). Select the method carefully by referring to the data sheet of the external SerDes.

The example design provided with the core only gives one of these methods (which vary on a family-by-family basis). However, the example HDL design can be edited to convert to the alternative method. See the following two methods for a Kintex 7 device.