Figure 1. Clock Management, Multiple Core Instances with the TBI
The above figure shows sharing clock resources across multiple instantiations of the
core when using the TBI. For all implementations, gtx_clk can be shared
between multiple cores, resulting in a common clock domain across the device.
The receiver clocks pma_rx_clk0 and pma_rx_clk1 (if
used) cannot be shared. Each core is provided with its own versions of these receiver
clocks from its externally connected SerDes.
The figure shows only two cores. However, more can be added using the same principle.
This is done by instantiating the cores using the block level (from the example design)
and sharing gtx_clk across all instantiations. The receiver clock logic
cannot be shared and must be unique for every instance of the core.