Clock Sharing across Multiple Cores with the TBI - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English
Figure 1. Clock Management, Multiple Core Instances with the TBI Ethernet 1000BASE-X PCS/PMA or SGMII Page-1 Sheet.1 Sheet.2 Block Level Block Level Sheet.3 Sheet.4 1G/2.5G Ethernet PCS/PMA or SGMII Core 1G/2.5G Ethernet PCS/PMA or SGMII Core Sheet.5 1G/2.5G Ethernet PCS/PMA or SGMII Core 1G/2.5G Ethernet PCS/PMA or SGMII Core Sheet.6 BUFIO BUFIO Sheet.7 BUFR BUFR Sheet.8 pma_rx_clk0#1 pma_rx_clk0#1 Sheet.9 Sheet.10 Sheet.11 pma_rx_clk0 pma_rx_clk0 Sheet.12 BUFR BUFR Sheet.13 pma_rx_clk1#1 pma_rx_clk1#1 Sheet.14 pma_rx_clk1 pma_rx_clk1 Sheet.15 Sheet.16 Customer Design Customer Design Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 gtx_clk gtx_clk Sheet.22 pma_rx_clk0#2 pma_rx_clk0#2 Sheet.23 pma_rx_clk1#2 pma_rx_clk1#2 Sheet.24 Sheet.25 Sheet.26 B B Sheet.27 UFG UFG Sheet.28 gtx_clk (125MHz) gtx_clk(125MHz) Sheet.29 Block Level Block Level Sheet.30 BUFIO BUFIO Sheet.31 X12827 X12827 Connector Dot Standard Arrow.19 Sheet.34 Connector Dot.14 Standard Arrow.11 Sheet.37 Sheet.38 Standard Arrow.15 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 BUFIO BUFIO Sheet.45 BUFR BUFR Sheet.46 Sheet.47 Sheet.48 pma_rx_clk0 pma_rx_clk0 Sheet.49 BUFR BUFR Sheet.50 pma_rx_clk1 pma_rx_clk1 Sheet.51 Sheet.52 Sheet.53 gtx_clk gtx_clk Sheet.54 BUFIO BUFIO Connector Dot.50 Standard Arrow.51 Sheet.57 Sheet.58 Standard Arrow.55 Sheet.60 Sheet.61 Sheet.62

The above figure shows sharing clock resources across multiple instantiations of the core when using the TBI. For all implementations, gtx_clk can be shared between multiple cores, resulting in a common clock domain across the device.

The receiver clocks pma_rx_clk0 and pma_rx_clk1 (if used) cannot be shared. Each core is provided with its own versions of these receiver clocks from its externally connected SerDes.

The figure shows only two cores. However, more can be added using the same principle. This is done by instantiating the cores using the block level (from the example design) and sharing gtx_clk across all instantiations. The receiver clock logic cannot be shared and must be unique for every instance of the core.