This module converts 1-bit serial data to 10-bits parallel data. It instantiates the I/O logic cells (IDELAYE3, ISERDES), delay controller and 4-bit to 10-bit gearbox functionality.
The following file describes the serdes 1 to 10 logic:
<project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/synth/sgmii_lvds_transceiver/<component_name>_serdes_1_to_10_ser8.v