Transceiver Implementation - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

The following figure shows the connections and clock management logic required to interface the core (in SGMII Configuration and MAC mode with the GTX/GTH transceiver) to the TEMAC core for Zynq 7000, Virtex 7 and Kintex 7 devices. The next figure shows the same interface for Artix 7 devices. The transceiver implementation is similar in 2.5G mode.

Figure 1. Core Using SGMII with the GTX/GTH Transceiver Connected to the TEMAC Core
Figure 2. Core Using SGMII with Artix 7 Transceiver Connected to the TEMAC Core

Features of this configuration include:

  • Observe that the block level of the TEMAC is instantiated. This provides the MAC with extra functionality that is not provided by the TEMAC core netlist. When using the MAC to connect the 1000BASE-X core, the “Internal” PHY interface mode must be selected from the TEMAC Vivado IDE prior to core generation. See the Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051).
  • The SGMII Adaptation module, as provided in the example design for the core when generated to the SGMII standard and MAC mode, can be used to interface the two cores.
  • If both cores have been generated with the optional management interface, the MDIO port can be connected up to that of the TEMAC core, allowing the MAC to access the embedded configuration and status registers of the 1G/2.5G Ethernet PCS/PMA or SGMII core.
  • Because of the receive elastic buffer, the entire GMII (transmitter and receiver paths) is synchronous to a single clock domain. Therefore, userclk2 is used as the 125 MHz reference clock for both cores, and the transmitter and receiver logic of the TEMAC core now operate in the same clock domain.