Core Overview - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
Release Date
16.2 English

This product guide provides information for generating a 1000BASE-X or 2500BASE-X Ethernet Physical Coding Sublayer/Physical Medium Attachment (PCS/PMA) or a Serial Gigabit Media Independent Interface (SGMII) or 2.5G SGMII core, customizing and simulating the core using the provided example design, and running the design files through implementation using AMD tools. The two standards supported are sufficiently similar to be supported in the same core.

The 1G/2.5G Ethernet PCS/PMA or SGMII IP core is a fully-verified solution that supports Verilog Hardware Description Language (HDL) and Very-High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL). In addition, the example design provided with the core supports both Verilog and VHDL.

For detailed information about the core, see the 1G/2.5G Ethernet PCS/PMA or SGMII product page.