SGMII/Dynamic Switching Using a Transceiver Example Design - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

The following figure shows an example design for top level HDL for the core in SGMII (or dynamic switching) mode using a device-specific transceiver / architecture, , or devices). Dynamic switching is not supported in 2.5G mode. The 2.5G SGMII mode structure is the same as that of 1G SGMII.

Figure 1. Example Design HDL in 1G or 2.5G SGMII Mode Using a Device-Specific Transceiver

The top level of the example design creates a specific example which can be simulated, synthesized and implemented. The top level of the example design performs the following functions:

  • Instantiates the block level HDL
  • Instantiates shared logic if shared logic in the example design is selected (see Shared Logic for more information)
  • Clock management logic for the core and the device-specific transceiver, including DCM (if required) and Global Clock Buffer instances
  • External GMII logic, including IOB and DDR register instances, where required