Clock Sharing Across Multiple Cores with Transceivers - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
PG047
Release Date
2023-11-01
Version
16.2 English
One instance of the core is generated with the Include Shared Logic in Core option. This instance contains all the clocking logic that can be shared. The remaining instances can be generated using the Include Shared Logic in Example Design option.

The following figure shows sharing clock resources across two instantiations of the core for AMD Virtex™ 7, AMD Kintex™ 7 and Zynq 7000 device transceivers; Figure 2 shows the connections for AMD Artix™ 7 devices. The following table shows example connections when connecting an instance generated with Include Shared Logic in Core to an instance generated using Include Shared Logic in Example Design. The clock frequencies specified in the diagrams are for 1G mode.

Additional cores can be added by continuing to instantiate extra block level modules. To provide the FPGA logic clocks for all core instances, select a txoutclk port from any transceiver and route this to a single MMCM. The clkout0 (125 MHz for 1 Gbps, 312.5 MHz for 2.5 Gbps) and clkout1 (62.5 MHz for 1 Gbps, 156.25 MHz for 2.5 Gbps) outputs from this MMCM, placed onto global clock routing using BUFGs, can be shared across all core instances and transceivers as shown.

Figure 1. Clock Management-Multiple Core Instances (Virtex 7, Kintex 7, Zynq 7000)

For UltraScale+/UltraScale devices the MMCM is not required because the txoutclk generated is 125 MHz for 1 Gbps, 312.5 MHz for 2.5 Gbps and can be used to generate the 62.5 MHz for 1 Gbps, 156.25 MHz for 2.5 Gbps (txuserclk) clock using the BUFG_GT. The same txoutclk can be used by other instances of the core by using the BUFG_GT as shown in Figure 3.

Figure 2. Clock Management-Multiple Core Instances (Artix 7)
Table 1. Shared Signals Connectivity
From Instance Using Shared Logic in Core To Instance Using Shared Logic in Example Design Design Considerations
gtrefclk_out gtrefclk GTREFCLK can be shared up one quad and down one quad
gtrefclk_bufg_out gtrefclk_bufg This is applicable only for 7 series and Zynq devices.
userclk_out userclk This can be shared only when TXOUTCLK (and hence gtrefclk) of both instances are synchronous; otherwise this should be connected to the TXOUTCLK port of the same instance (For 1G mode). This clock frequency is 62.5 MHz in 1 Gbps mode, 156.25 MHz in 2.5 Gbps mode. This clock can be used across the whole device and is used for any GT that has the same gtrefclk
userclk2_out userclk2 This can be shared only when TXOUTCLK (and hence gtrefclk) of both the instances are synchronous; otherwise this should be connected to TXOUTCLK multiplied by two (for 1G mode) of the same instance. This clock frequency is 125 MHz in 1 Gbps mode, 312.5 MHz in 2.5 Gbps mode. This clock can be used across the whole device and used for any GT that has the same gtrefclk.
rxuserclk_out rxuserclk This can be shared only when RXOUTCLK (recovered clock) of both the channels are synchronous; otherwise this should be connected to the RXOUTCLK port of the same instance. This clock frequency is 62.5 MHz in 1 Gbps mode, 156.25 MHz in 2.5 Gbps mode.
rxuserclk2_out rxuserclk2 This can be shared only when the RXOUTCLK signal (recovered clock) of both the channels are synchronous. Otherwise this should be connected to the RXOUTCLK port of the same instance. This clock frequency is 62.5 MHz in 1 Gbps mode and 156.25 MHz in 2.5 Gbps mode. The frequency of this clock when RxGmiiClkSrc=RXOUTCLK is 125 MHz and 312.5 MHz respectively.
pma_reset_out pma_reset
mmcm_locked_out mmcm_locked Provided both the instances use the same MMCM.
GTH/GTX Transceiver Specific Signals
gt0_qplloutclk_out gt0_qplloutclk_in Common block output connections for cores in same Quad 1
gt0_qplloutrefclklost_out gt0_qplloutrefclklost_in
GTP Transceiver Specific Signals
gt0_pll0outclk_out gt0_pll0outclk_in Common block output connections for cores in same Quad 1
gt0_pll0outrefclk_out gt0_pll0outrefclk_in
gt0_pll1outclk_out gt0_pll1outclk_in
gt0_pll1outrefclk_out gt0_pll1outrefclk_in
gt0_pll0lock_out gt0_pll0lock_in
gt0_pll0refclklost_out gt0_pll0refclklost_in
  1. If instances are using more than one QUAD then an extra common block can be instantiated for each extra quad and connected to each core in that quad.