SGMII Standard without Optional Auto-Negotiation - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

The registers provided for SGMII operation in this core are adaptations of those defined in clauses 22 and 37 of the IEEE 802.3-2008 specification. In an SGMII implementation, two different types of links exist. They are the SGMII link between the MAC and PHY (SGMII link) and the link across the Ethernet Medium itself (Medium). See Using the SGMII MAC Mode to Interface to an External BASE-T PHY with SGMII Interface. Information about the state of the SGMII link is available in registers that follow. For 2.5G SGMII the register definition is similar to 1G SGMII. Speed selection bits in 2.5G mode are not relevant because the core supports only 2.5G.

Important: The state of the link across the Ethernet medium itself is not directly available when SGMII Auto-Negotiation is not present. For this reason, the status of the link and the results of the PHYs Auto-Negotiation (for example, Speed and Duplex mode) must be obtained directly from the management interface of connected PHY module. Registers at undefined addresses are read-only and return 0s.

The core can be reset three ways: reset, DCM_LOCKED and soft reset. All of these methods reset all the registers to the default values.

Table 1. MDIO Registers for SGMII with Auto-Negotiation
Register Address Register Name
0 Register 0: Control Register
1 Register 1: Status Register
2,3 Registers 2 and 3: PHY Identifiers
15 Register 15: SGMII Extended Status