Requirement for the Receive Elastic Buffer - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

The following figure shows a simplified diagram of a common situation where the core, in SGMII mode, is interfaced to an external PHY device. Separate oscillator sources are used for the FPGA and the external PHY. The Ethernet specification uses clock sources with a tolerance of 100 ppm. In the following figure, the clock source to the PHY is slightly faster than the clock source to the FPGA. For this reason, during frame reception, the receive elastic buffer (shown here as implemented in the device-specific transceiver) starts to fill.

Following frame reception, in the interframe gap period, idles are removed from the received data stream to return the receive elastic buffer to half-full occupancy. This is performed by the clock correction circuitry (see the device-specific transceiver user guide for the targeted device). The receive elastic buffer also performs clock correction on C1,C2 configuration code words received during auto-negotiation. This is similar to the way that clock correction is done on C1 in the transceiver elastic buffer.

Figure 1. SGMII Implementation Using Separate Clock Sources Ethernet 1000BASE-X PCS/PMA or SGMII Page-1 Sheet.1 FPGA FPGA Sheet.2 1G/2.5G Ethernet PCS/PMA or SGMII Core 1G/2.5G Ethernet PCS/PMA or SGMII Core Sheet.3 Transceiver Transceiver Sheet.4 RX Elastic Buffer RXElasticBuffer Sheet.6 10BASE-T 100BASE-T 1000BASE-T PHY 10BASE-T100BASE-T1000BASE-TPHY Sheet.7 RXP/RXN RXP/RXN Sheet.8 Sheet.9 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 125 MHz -100 ppm 125 MHz -100 ppm Sheet.18 Twisted Copper Pair TwistedCopperPair Sheet.19 TXP/TXN TXP/TXN Sheet.20 SGMII Link SGMII Link Standard Arrow.19 Standard Arrow.8 Standard Arrow.9 Standard Arrow.10 Sheet.27 X12862 X12862 Sheet.28 Sheet.5 Sheet.10 125 MHz -100 ppm 125 MHz -100 ppm

Assuming separate clock sources, each of tolerance 100 ppm, the maximum frequency difference between the two devices can be 200 ppm. It can be shown that this translates into a full clock period difference every 5000 clock periods.

Relating this to an Ethernet frame, there is a single byte of difference for every 5000 bytes of received frame data, which causes the receive elastic buffer to either fill or empty by an occupancy of one.

The maximum Ethernet frame size (non-jumbo) is 1522 bytes for a Virtual Local Area Network (VLAN) frame.

  • At 1 Gbps operation, this translates into 1522 clock cycles.
  • At 100 Mbps operation, this translates into 15220 clock cycles (as each byte is repeated 10 times).
  • At 10 Mbps operation, this translates into 152200 clock cycles (as each byte is repeated 100 times).

Considering the 10 Mbps case, you need 152200/5000 = 31 FIFO entries in the elastic buffer above and below the half way point to guarantee that the buffer does not under or overflow during frame reception. This assumes that frame reception begins when the buffer is exactly half full.

The size of the receive elastic buffer in the device-specific transceivers is 64 entries. However, you cannot assume that the buffer is exactly half full at the start of frame reception. Additionally, the underflow and overflow thresholds are not exact (see Receive Elastic Buffer Specifications for more information).

To guarantee reliable SGMII operation at 10 Mbps (non-jumbo frames), the device-specific transceiver elastic buffer must be bypassed and a larger buffer implemented in the FPGA logic. The FPGA logic buffer, provided by the example design, is twice the size of the device-specific transceiver alternative. This has been proven to cope with standard (none jumbo) Ethernet frames at all three SGMII speeds.

Receive Elastic Buffer Specifications provides further information about all receive elastic buffer used by the core. Information about the reception of jumbo frames is also provided.