Asynchronous 1000BaseX/SGMII over LVDS Example Design (Versal Devices) - 16.2 English - PG047

The following figure shows The Example design provided for Asynchronous 1000BaseX/SGMII over Versal device LVDS Implementation. Logic to generate Input clocks (125 MHz Core Clock, PLL input clock and CTRL clock) for the core and the RIU reset state machine are provided in the example design.