Ten-Bit Interface Implementation - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

shows the connections and clock management logic required to interface the core (in SGMII mode with the TBI) to the TEMAC core. The 2.5G mode is not supported in TBI mode.

Important: The TEMAC core must be generated with “interface” variable set as “Internal” for interfacing with 1G/2.5G Ethernet PCS/PMA or SGMII core.
Features of this configuration include:
  • The SGMII Adaptation module, provided in the example design for the core when generated to the SGMII standard, can be used to interface the two cores.
  • If both cores have been generated with the optional management interface, the MDIO port can be connected to that of the TEMAC core, allowing the MAC to access the embedded configuration and status registers of the 1G/2.5G Ethernet PCS/PMA or SGMII core.
Figure 1. Core Using TBI Connected to the TEMAC Core