Ten-Bit Interface Implementation - 16.2 English - PG047

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
PG047
Release Date
2023-11-01
Version
16.2 English

shows the connections and clock management logic required to interface the core (in SGMII mode with the TBI) to the TEMAC core. The 2.5G mode is not supported in TBI mode.

Important: The TEMAC core must be generated with “interface” variable set as “Internal” for interfacing with 1G/2.5G Ethernet PCS/PMA or SGMII core.
Features of this configuration include:
  • The SGMII Adaptation module, provided in the example design for the core when generated to the SGMII standard, can be used to interface the two cores.
  • If both cores have been generated with the optional management interface, the MDIO port can be connected to that of the TEMAC core, allowing the MAC to access the embedded configuration and status registers of the 1G/2.5G Ethernet PCS/PMA or SGMII core.
Figure 1. Core Using TBI Connected to the TEMAC Core Ethernet 1000BASE-X PCS/PMA or SGMII Page-1 Sheet.1 Tri-Mode Ethernet MAC Core Tri-Mode Ethernet MAC Core Sheet.2 <component_name>_block <component_name>_block Sheet.3 1G/2.5G Ethernet PCS/PMA or SGMII Core 1G/2.5G EthernetPCS/PMAor SGMIICore Sheet.4 gmii_rxd[7:0] gmii_rxd[7:0] Sheet.5 gmii_rx_dv gmii_rx_dv Sheet.6 gmii_rx_er gmii_rx_er Sheet.7 gmii_txd[7:0] gmii_txd[7:0] Sheet.8 gmii_tx_en gmii_tx_en Sheet.9 gmii_tx_er gmii_tx_er Sheet.10 mdc mdc Sheet.11 mdio_in mdio_in Sheet.12 mdio_out mdio_out Sheet.13 Sheet.14 mdio_tri mdio_tri Sheet.15 Sheet.16 Sheet.17 no no Sheet.18 connection connection Sheet.19 userclk2 userclk2 Sheet.20 gtx_clk gtx_clk Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 IP IP Sheet.27 AD AD Sheet.28 Sheet.29 Sheet.30 IBUFG IBUFG Sheet.32 Sheet.33 IOB LOGIC IOB LOGIC Sheet.34 gtx_clk gtx_clk Sheet.35 Sheet.36 BUFG BUFG Sheet.37 Sheet.38 TBI TBI Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 Sheet.49 gmii_txd[7:0] gmii_txd[7:0] Sheet.50 Sheet.51 Sheet.52 gtx_clk gtx_clk Sheet.53 Sheet.54 Sheet.55 Sheet.56 gmii_tx_en gmii_tx_en Sheet.57 gmii_tx_er gmii_tx_er Sheet.58 gmii_rxd[7:0] gmii_rxd[7:0] Sheet.59 gmii_rx_dv gmii_rx_dv Sheet.60 gmii_rx_er gmii_rx_er Sheet.61 mdc mdc Sheet.62 mdio_tri mdio_tri Sheet.63 mdio_in mdio_in Sheet.64 mdio_out mdio_out Sheet.65 X12773 X12773 Sheet.66 MAC AX14-Stream I/F MACAX14-StreamI/F Standard Arrow.143 Standard Arrow.142 Sheet.69 AX14-Lite to IPIF AX14-Liteto IPIF Standard Arrow.66 Standard Arrow.67 Sheet.72 Sheet.73 SGMII Adaptation Module SGMII AdaptationModule Sheet.74 gmii_rxd_in[7:0] gmii_rxd_in[7:0] Sheet.75 gmii_rx_dv_in gmii_rx_dv_in Sheet.76 gmii_rx_er_in gmii_rx_er_in Sheet.77 gmii_txd_out[7:0] gmii_txd_out[7:0] Sheet.78 gmii_tx_en_out gmii_tx_en_out Sheet.79 gmii_tx_er_out gmii_tx_er_out Sheet.80 gmii_rxd_out[7:0] gmii_rxd_out[7:0] Sheet.81 gmii_rx_dv_out gmii_rx_dv_out Sheet.82 gmii_rx_er_out gmii_rx_er_out Sheet.83 gmii_txd_in[7:0] gmii_txd_in[7:0] Sheet.84 gmii_tx_en_in gmii_tx_en_in Sheet.85 gmii_tx_er_in gmii_tx_er_in Sheet.86 Sheet.87 Sheet.88 Sheet.89 sgmii_clk_en sgmii_clk_en Sheet.90 sgmii_clk_r sgmii_clk_r Sheet.91 speed_is_10_100 speed_is_10_100 Sheet.92 Sheet.93 speed_is_100 speed_is_100 Sheet.94 NC NC Sheet.95 Sheet.96 clk125 clk125 Sheet.97 clk_enable clk_enable Sheet.98 speedis10100 speedis10100 Sheet.99 speedis100 speedis100 Sheet.100 Sheet.101 Connector Dot Connector Dot.101 Sheet.104 Sheet.105 Sheet.106 Statistics Vectors Interface Statistics Vectors Interface Standard Arrow.105