The following figure shows an external GMII receiver created in a 7 series device. The
signal names and logic shown in the figure exactly match those delivered with the
example design when the GMII is selected. If other families are selected, equivalent
primitives and logic specific to that family is automatically used in the example
design.
The following figure also shows that the output receiver signals are registered in device
IOBs before driving them to the device pads. The logic required to forward the receiver
GMII clock is also shown. This uses an IOB output Double-Data-Rate (DDR) register so
that the clock signal produced incurs exactly the same delay as the data and control
signals. This clock signal, gmii_rx_clk, is inverted so that the rising
edge of gmii_rx_clk occurs in the center of the data valid window,
which maximizes setup and hold times across the interface. All receiver logic is
synchronous to a single clock domain.