GMII Receiver Logic - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

The following figure shows an external GMII receiver created in a 7 series device. The signal names and logic shown in the figure exactly match those delivered with the example design when the GMII is selected. If other families are selected, equivalent primitives and logic specific to that family is automatically used in the example design.

The following figure also shows that the output receiver signals are registered in device IOBs before driving them to the device pads. The logic required to forward the receiver GMII clock is also shown. This uses an IOB output Double-Data-Rate (DDR) register so that the clock signal produced incurs exactly the same delay as the data and control signals. This clock signal, gmii_rx_clk, is inverted so that the rising edge of gmii_rx_clk occurs in the center of the data valid window, which maximizes setup and hold times across the interface. All receiver logic is synchronous to a single clock domain.

The clock name varies depending on the core configuration options. When used with the device-specific transceiver, the clock name is userclk2; when used with the TBI, the clock name is gtx_clk. For more information on clocking, see Asynchronous LVDS Transceiver for Versal devices, and SGMII/Dynamic Switching with Transceivers.

Figure 1. External GMII Receiver Logic Ethernet 1000BASE-X PCS/PMA or SGMII Page-1 Sheet.83 userclk2 (if transceiver is used) userclk2 (if transceiver is used) Sheet.3 IOB LOGIC IOB LOGIC Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 OBUFT OBUFT Sheet.10 ODDR ODDR Sheet.11 OPAD OPAD Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 gmii_rxd_obuf[0] gmii_rxd_obuf[0] Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE 1G/2.5G Ethernet PCS/PMAor SGMII LogiCORE Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 OPAD OPAD Sheet.49 OPAD OPAD Sheet.50 OPAD OPAD Sheet.51 OBUFT OBUFT Sheet.52 OBUFT OBUFT Sheet.53 OBUFT OBUFT Sheet.54 D D Sheet.55 Q Q Sheet.56 D D Sheet.57 Q Q Sheet.58 D D Sheet.59 Q Q Sheet.60 gmii_rx_dv_obuf gmii_rx_dv_obuf Sheet.61 gmii_rx_er_obuf gmii_rx_er_obuf Sheet.62 gmii_rxd[0] gmii_rxd[0] Sheet.63 gmii_rx_dv gmii_rx_dv Sheet.64 gmii_rx_er gmii_rx_er Sheet.65 gmii_rx_clk gmii_rx_clk Sheet.66 gmii_rx_clk_obuf gmii_rx_clk_obuf Sheet.67 gmii_rxd[0] gmii_rxd[0] Sheet.68 gmii_rx_dv gmii_rx_dv Sheet.69 gmii_rx_er gmii_rx_er Sheet.70 gmii_isolate gmii_isolate Sheet.71 Sheet.72 Sheet.73 Sheet.74 Sheet.75 Sheet.76 Sheet.77 Sheet.78 Sheet.79 Sheet.80 Sheet.81 Sheet.82 Sheet.84 gtx_clk (if TBI is used) gtx_clk (if TBI is used) Sheet.85 X12791 X12791 Sheet.86 Sheet.87 Sheet.88 Sheet.89 Sheet.90