Asynchronous LVDS Clocking and Reset logic (Versal Devices) - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
Release Date
16.2 English

Asynchronous LVDS solution for Versal implements the Advanced IO Wizard as a sub-core. An XPLL that is included within Advanced IO Wizard sub-core, is used to provide clocking to RX Gearbox, TX Gearbox and blocks present within the wizard. The XPLL generates clocks of frequencies 312.5 MHz and 1250Mhz, a 312.5Mhz clock output is connected to a BUFGCE_DIV to provide clocking to TX gearbox at 156.25Mhz.

The core supports up to three instances of PCS/PMA lanes to be used with a single instance of Advanced IO Wizard. As XPLL cannot be shared across the core instances, the maximum number of single/multi-lane cores supported per IO bank is 2.

Shareable logic includes the clocking logic to generate clk125m, pll_clk_in and ctrl_clk along with an RIU based reset state machine. The shareable logic mentioned above is always included in the example design.