Integration of the Zynq 7000 Device PS ENET0/1 for 1000BASE-X Operation - 16.2 English

The following figure shows the connections and clock management logic required to interface the core (in 1000BASE-X mode) to the Zynq 7000 device PS ENET0/1. The 2.5G mode is not supported in this case.

Features of this configuration include:

• Direct internal connections are made between the GMII interfaces between the ENET0/1 and 1G/2.5G Ethernet PCS/PMA or SGMII core.
• The MDIO port can be connected, allowing the Ethernet MAC to access the embedded configuration and status registers of the 1G/2.5G Ethernet PCS/PMA or SGMII core.
• Because of the embedded receive elastic buffer in the transceiver, the entire GMII is synchronous to a single clock domain. Therefore, userclk2 is used as the 125 MHz reference clock for both ENET0/1 and 1G/2.5G Ethernet PCS/PMA or SGMII core, and the transmitter and receiver logic of the Zynq 7000 device PS ENET0/1 now operate in the same clock domain.