For 1000BASE-X - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English
The following figure shows the receive elastic buffer depth and thresholds when using the Ten-Bit Interface with the 1000BASE-X standard. This buffer is intentionally smaller than the equivalent buffer for SGMII/Dynamic Switching. Because a larger size is not required, the buffer is kept smaller to save logic and keep latency low. Each FIFO word corresponds to a single character of data (equivalent to a single byte of data following 8B/10B decoding).
Figure 1. TBI Elastic Buffer Size for All Families Ethernet 1000BASE-X PCS/PMA or SGMII Page-1 Sheet.1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 32 32 Sheet.7 Sheet.15 Sheet.16 Sheet.17 Sheet.18 18 18 Sheet.34 TBI RX Elastic Buffer TBIRX Elastic Buffer Sheet.38 Sheet.39 14 14 Sheet.19 30 – Overflow Mark 30 – Overflow Mark Sheet.20 2 – Underflow Mark 2 – Underflow Mark Sheet.8 Sheet.9 X12870 X12870

The shaded area of the previous figure represents the usable buffer availability for the duration of frame reception.

  • If the buffer is filling during frame reception, then there are 30-18 = 12 FIFO locations available before the buffer reaches the overflow mark.
  • If the buffer is emptying during reception, then there are 14-2 = 12 FIFO locations available before the buffer reaches the underflow mark.

This analysis assumes that the buffer is approximately at the half-full level at the start of the frame reception. As shown, there are two locations of uncertainty above and below the exact half-full mark of 16. This is as a result of the clock correction decision, and is based across an asynchronous boundary.

Because there is a worst-case scenario of 1 clock edge difference every 5000 clock periods, the maximum number of clock cycles (bytes) that can exist in a single frame passing through the buffer before an error occurs is:

5000 x 12 = 60000 bytes

This translates into a maximum frame size of 60000 bytes.