The following figure shows the HDL example design that is provided for the
Asynchronous 1000BASE-X/SGMII over UltraScale and UltraScale+ device LVDS implementation. The top level of the example
design creates a specific example that can be simulated, synthesized and implemented.
The 2.5G mode is not supported in this case. The core netlist in this implementation is
identical to that of 1G/2.5G Ethernet PCS/PMA or SGMII Using a Device-Specific
Transceiver.
Figure 1. Example Design for Asynchronous 1000BASE-X/SGMII over LVDS