GMII Ports - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)
Document ID
PG047
Release Date
2023-11-01
Version
16.2 English

The following table describes the core GMII interface ports common to all core configurations. These are typically attached to an Ethernet MAC, either off-chip or internally integrated. The HDL block level design delivered with the core connects these signals to IOBs. For more information, see Using the Client-Side GMII Datapath.

Table 1. GMII Interface Signal Pinout
Signal Direction Description
gmii_txd[7:0] 1 Input GMII Transmit data from MAC.
gmii_tx_en 1 Input GMII Transmit control signal from MAC.
gmii_tx_er 1 Input GMII Transmit control signal from MAC.
gmii_rxd[7:0] 2 Output GMII Received data to MAC.
gmii_rx_dv 2 Output GMII Received control signal to MAC.
gmii_rx_er 2 Output GMII Received control signal to MAC.
gmii_isolate 2 Output IOB 3-state control for GMII Isolation. Only of use when implementing an External GMII as shown by the block level design HDL.
  1. When the TX elastic buffer is present, these signals are synchronous to gmii_tx_clk. When the TX elastic buffer is omitted, see 2 .
  2. These signals are synchronous to the internal 125 MHz reference clock of the core. This is userclk2 when the core is used with the device-specific transceiver; gtx_clk when the core is used with TBI.