The registers provided for SGMII operation in this core are adaptations of those defined in
clauses 22 and 37 of the IEEE 802.3-2008 specification. In an SGMII implementation,
two different types of links exist. They are the SGMII link between the MAC and PHY
(SGMII link) and the link across the Ethernet Medium itself (Medium). See Using the SGMII MAC Mode to Interface to an External BASE-T PHY with SGMII Interface.
Information regarding the state of both of these links is contained within the following registers. Where applicable, the abbreviations SGMII link and Medium are used in the register descriptions. Registers at undefined addresses are read-only and return 0s. The core can be reset three ways: reset, DCM_LOCKED and soft reset. All of these methods reset all the registers to the default values. For 2.5G SGMII the register definition is similar to 1G SGMII. Speed selection bits in 2.5G mode are not relevant because the core supports only 2.5G.
Register Address | Register Name |
---|---|
0 | Register 0: Control Register |
1 | Register 1: Status Register |
2,3 | Registers 2 and 3: PHY Identifiers |
4 | Register 4: Auto-Negotiation Advertisement |
5 | Register 5: Auto-Negotiation Link Partner Base |
6 | Register 6: Auto-Negotiation Expansion |
7 | Register 7: Auto-Negotiation Next Page Transmit |
8 | Register 8: Auto-Negotiation Next Page Receive |
15 | Register 15: Extended Status |
16 | Register 16: Vendor-Specific Auto-Negotiation Interrupt Control |