SGMII FPGA Logic Receive Elastic Buffer - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)
Document ID
PG047
Release Date
2023-11-01
Version
16.2 English

The following figure shows the FPGA logic receive elastic buffer depth. This buffer can optionally be used to replace the receive elastic buffers of the transceiver when performing SGMII or Dynamic Switching (see Receive Elastic Buffer).

Figure 1. Elastic Buffer Size for All Transceiver Families Ethernet 1000BASE-X PCS/PMA or SGMII Page-1 Sheet.1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 128 128 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 66 66 Sheet.12 SGMII FPGA Fabric RX Elastic Buffer SGMII FPGA FabricRX Elastic Buffer Sheet.13 Sheet.14 62 62 Sheet.15 122 – Overflow Mark 122 – Overflow Mark Sheet.16 6 – Underflow Mark 6 – Underflow Mark Sheet.17 Sheet.18 X12861 X12861

The shaded area of the orevious figure represents the usable buffer availability for the duration of frame reception.

  • If the buffer is filling during frame reception, there are 122-66 = 56 FIFO locations available before the buffer reaches the overflow mark.
  • If the buffer is emptying during reception, then there are 62-6 = 56 FIFO locations available before the buffer reaches the underflow mark.

This analysis assumes the buffer is approximately at the half-full level at the start of the frame reception. As shown, there are two locations of uncertainty, above and below the exact half-full mark of 64. This is as a result of the clock correction decision, and is based across an asynchronous boundary.

Because there is a worst-case scenario of one clock edge difference every 5000 clock periods, the maximum number of clock cycles (bytes) that can exist in a single frame passing through the buffer before an error occurs is:

5000 x 56 = 280000 bytes

The following figure translates this into maximum frame size at different Ethernet speeds. At SGMII speeds lower than 1 Gbps, performance is diminished because bytes are repeated multiple times. See Using the Client-Side GMII for the SGMII Standard.

Table 1. Maximum Frame Sizes: FPGA logic Receive Elastic Buffers (100 ppm Clock Tolerance)
Standard/Speed Maximum Frame Size (Bytes)
1000BASE-X (1 Gbps only) 280000
SGMII (1 Gbps) 280000
SGMII (100 Mbps) 28000
SGMII (10 Mbps) 2800