Idle Character Removal at 10 Mbps (SGMII) - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
Release Date
16.2 English

Using a similar argument to the 100 Mbps case, it can be shown that clock correction circuitry can also cope with a frame size up to 20000 bytes. However, this is larger than the maximum frame size for any elastic buffer provided with the core (see Receive Elastic Buffers: Depths and Maximum Frame Sizes).