- NumOfLanes
- Number of PCS/PMA lanes to generate. This is applicable only for asynchronous 1000BASE-X/SGMII over LVDS.
- TxLane0_Placement
- This is the location of txp_0/txn_0 within TxNibble. Valid values are:
- DIFF_PAIR_0
- Indicates bitslice0 and bitslice1 to be used for the first lane.
- DIFF_PAIR_1
- Indicates bitslice2 and bitslice3 to be used for the first lane.
- DIFF_PAIR_2
- Indicates bitslice4 and bitslice5 to be used for the first lane.
- TxLane1_Placement
- This is the location of txp_1/txn_1 within TxNibble (if Number_of_Lanes is
greater than 1). Valid values are:
- DIFF_PAIR_0
- Indicates bitslice0 and bitslice1 to be used for the second lane.
- DIFF_PAIR_1
- Indicates bitslice2 and bitslice3 to be used for the second lane.
- DIFF_PAIR_2
- Indicates bitslice4 and bitslice5 to be used for the second lane.
For the third lane the placement not selected for Lane 0 and Lane 1 is chosen.
- RxLane0_Placement
- This is the location of rxp_0/rxn_0 within RxNibble. Valid values are:
- DIFF_PAIR_0
- Indicates bitslice0 and bitslice1 to be used for the first lane.
- DIFF_PAIR_1
- Indicates bitslice2 and bitslice3 to be used for the first lane.
- DIFF_PAIR_2
- Indicates bitslice4 and bitslice5 to be used for the first lane.
- RxLane1_Placement
- This is the location of rxp_1/rxn_1 within RxNibble (if Number_of_Lanes is
greater than 1). Valid values are:
- DIFF_PAIR_0
- Indicates bitslice0 and bitslice1 to be used for the second lane.
- DIFF_PAIR_1
- Indicates bitslice2 and bitslice3 to be used for the second lane.
- DIFF_PAIR_2
- Indicates bitslice4 and bitslice5 to be used for the second lane.
For third lane the placement not selected for Lane 0 and Lane 1 would be chosen.
- InstantiateBitslice0
- This is an indication to the logic to instantiate a Dummy BITSLICE0.
If TRUE, then the core logic handles BITSLICE0 insertion. If BITSLICE0 insertion is required a dummy BITSLICE0 is instantiated, and a dummy_port_in appears at the top level (depending on the RxNibbleBitslice0Used value). The dummy_port_in needs to be connected at the top level and the pin LOC'ed at the appropriate BITSLICE0 location.
- RxNibbleBitslice0Used
- This is an indication to the core if the BITSLICE0 of RX_NIBBLE is used as the reference clock. This is enabled only when InstantiateBitslice0 is enabled.
- Tx_In_Upper_Nibble
- Indicates whether the TX is in the upper or lower nibble, If
Tx_In_Upper_Nibble=0 this means that the RX is in the upper nibble and the TX is
in lower nibble and vice versa.
Valid Values: 0/1