GT in Example Design - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

This option is available only if Include Shared logic in Example Design is selected. This moves the transceiver from the core to the Support level instance. When this option is selected generation of additional transceiver control and status ports is disabled. This option is available only for UltraScale architecture designs.

Note: For Versal, the GT is always in the example design.