Ports Added from v15.1 to v15.2 - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID: PG047
Release Date: 2023-11-01
Version: 16.2 English

Table 1. Ports Added in v15.2
In/Out	Port Name and Width	Description	What to do
Output	recclk_mmcm_reset	MMCM reset for MMCM generating rxuserclk, rxuserclk2, when RxGmiiClkSrc=RXOUTCLK. This is output only when the clocking logic is a part of the example design and applicable only for 7 series devices with MMCM is used for clock multiplication.	Connect to input signal of TEMAC when TEMAC is generated in internal mode and selecting RX clock source as RXOUTCLK.
Output	sgmii_rx_clk_r	Differential clock for GMII RX data when RxGmiiClkSrc=RXOUTCLK in SGMII mode.	Connect to input signal of TEMAC when TEMAC is generated in internal mode and selecting RX clock source as RXOUTCLK.
Output	sgmii_rx_clk_f	Differential clock for GMII RX data when RxGmiiClkSrc=RXOUTCLK in SGMII mode.	Connect to input signal of TEMAC when TEMAC is generated in internal mode and selecting RX clock source as RXOUTCLK.
Output	sgmii_rx_clk_en	Clock for GMII RX data	Connect to input signal of TEMAC when TEMAC is generated in internal mode and selecting RX clock source as RXOUTCLK.
All ports in		See the UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182) for a description of the ports.