Interfacing with Ethernet MAC Peripherals in Device PS - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

This module creates the sgmii_clk_en and sgmii_ddr_clk_en clock enable signals for use throughout the SGMII adaptation module. The following figure shows the clock enable signal for the Clock Generation module at 1 Gbps and 100 Mbps speeds.

Figure 1. Clock Enable Signal for the Clock Generation Module

The above figure also shows the formation of the sgmii_clk_r signal. sgmii_clk_r is forwarded to the Ethernet Mac Peripheral through gmii_tx_clk port and gmii_rx_clk port. This provides SGMII clock forwarding at the correct frequency.

  1. The sgmii_clk_f signal is not used in this case.
  2. The sgmii_clk_en is not provided as an output but used internally within the SGMII adaptation module.
The sgmii_clk_r frequencies for the different modes are:
  • 125 MHz at an operating speed of 1 Gbps
  • 25 MHz at an operating speed of 100 Mbps
  • 2.5 MHz at an operating speed of 10 Mbps