Receive Elastic Buffer - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
Release Date
16.2 English

This section describes the two receive elastic buffer implementations; one implementation uses the buffer present in the device-specific transceivers, and the other uses a larger buffer, implemented in FPGA logic. If the latter option is selected, the buffer in the device-specific transceiver is bypassed in UltraScale and UltraScale+ families. For 7 series devices the buffer in the device-specific transceiver is not bypassed; however it is read using the recovered clock.

The receive elastic buffer if present, is described in the following files:

<project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/ synth/transceiver/<component_name>_rx_elastic_buffer.v[hd]

If the transceiver buffer is bypassed, the buffer implemented in the FPGA logic is instantiated from within the transceiver wrapper. This alternative receive elastic buffer uses a single block RAM to create a buffer twice as large as the one present in the device-specific transceiver, and is able to cope with larger frame sizes before clock tolerances accumulate and result in an emptying or filling of the buffer.