Although the 1G/2.5G Ethernet PCS/PMA or SGMII core is a fully-verified solution, the challenge associated with implementing a complete design varies depending on the configuration and functionality of the application. For best results, previous experience building high-performance, pipelined Field Programmable Gate Array (FPGA) designs using AMD implementation software with the Xilinx Design Constraints (XDC) is recommended.
Contact your local representative for a closer review and estimation for your specific requirements.