Synchronous SGMII LVDS Transceiver for UltraScale Devices - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

The LVDS transceiver block fully replaces the functionality otherwise provided by an UltraScale device transceiver. This is only possible at a serial line rate of 1.25 Gbps. The LVDS is split up into several sub-blocks which are described in further detail in the following sections.

The following figure shows a block diagram of the synchronous LVDS transceiver for UltraScale devices. This is split up into several sub-blocks which are described in further detail in the following sections.

Figure 1. LVDS Transceiver Block Level for UltraScale Devices Ethernet 1000BASE-X PCS/PMA or SGMII Page-1 Sheet.4 Sheet.10 Sheet.12 8B10B Encoder 8B10BEncoder Sheet.21 Sheet.23 ISERDES_S ISERDES_S Sheet.45 <component_name>_lvds_transceiver_ser8 <component_name>_lvds_transceiver_ser8 Sheet.46 Sheet.47 <component_name>_serdes_1_to_10 <component_name>_serdes_1_to_10 Sheet.52 Delay Controller Delay Controller Sheet.56 idelay_cal idelay_cal Sheet.61 Sheet.63 ISERDES_M ISERDES_M Sheet.65 Sheet.67 IDELAY_S IDELAY_S Sheet.69 Sheet.71 IDELAY_M IDELAY_M Sheet.73 IBUFDS DIFF_OUT IBUFDSDIFF_OUT Sheet.109 <component_name>_serdes_10_to_1 <component_name>_serdes_10_to_1 Standard Arrow.563 Standard Arrow.114 Standard Arrow.115 Sheet.116 8B10B Decoder 8B10BDecoder Sheet.117 Gearbox 10_to_4 Gearbox 10_to_4 Sheet.118 OSERDES OSERDES Sheet.119 OBUFDS OBUFDS Standard Arrow.120 Standard Arrow.121 Standard Arrow.122 Standard Arrow.123 Standard Arrow.124 Sheet.125 Gearbox 4_to_10 Gearbox 4_to_10 Standard Arrow.126 Standard Arrow.127 Standard Arrow.128 Standard Arrow.129 Standard Arrow.130 Standard Arrow.131 Standard Arrow.132 Standard Arrow.133 Standard Arrow.134 Standard Arrow.135 Standard Arrow.136 Standard Arrow.137 Sheet.138 X22820-043019 X22820-043019

On the transmitter path, data sourced by the core netlist is routed through the 8B/10B Encoder to translate the 8-bit code groups into 10-bit data. The 10-bit data is then passed through the 10B4B Gearbox and the 4-bit parallel data is then clocked out serially at a line rate of 1.25 Gbps.

The receiver path has additional complexity. Serial data received at 1.25 Gbps is routed in parallel to two IODELAYE3 and ISERDESE3. The LVDS transceiver block uses the UltraScale device OSERDESE3, IODELAYE3s and ISERDESE3 elements. See the UltraScale Architecture SelectIO Resources User Guide (UG571) for a description of these elements. Logic is provided to find the correct sampling point in the delay controller block.

Then parallel data is fed to the 4B10B gearbox which converts it into 10-bit parallel data. Having recovered parallel data from the serial stream, comma alignment and detection is done on the parallel data. Receiver uses these to realign the 10-bit parallel data to contain unique 8B/10B code groups. These code groups are then routed through the 8B/10B Decoder module to obtain the unencoded 8-bit code groups that the core netlist can accept.

The following files describe the top level of the hierarchal levels of the LVDS transceiver:

<project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/synth /sgmii_lvds_transceiver/<component_name>_lvds_transceiver_ser8.v
Note: Transceiver functionality is implemented only in Verilog except for the 8B/10B encoder and 10B/8B decoder modules which are project setting specific.