RIU interface is used by BITSLICE_CONTROL primitives in Ultrascale and Ultrascale+ devices as well as by the XPHY in Versal devices.
| Signal | Direction | Description |
|---|---|---|
| riu_clk | Input |
Clock from interconnect logic. The RIU clock must be connected in for the BISC process to complete. (ctrl_clk Is used for clocking RIU in Versal devices). |
| riu_addr | Input | Register Address. |
| riu_wr_data[15:0] | Input | Data write to register. |
| riu_rd_data[15:0] | Output | Data read form register. |
| riu_valid | Output | Asserts when the user has control over the RIU bus. |
| riu_wr_en | Input | Active high register write enable. |
| riu_nibble_sel | Input |
Nibble in byte select. This signal must be High to perform read/write to the nibble. |