RIU Interface Ports - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

RIU interface is used by BITSLICE_CONTROL primitives in Ultrascale and Ultrascale+ devices as well as by the XPHY in Versal devices.

Table 1. RIU Interface Ports
Signal Direction Description
riu_clk Input

Clock from interconnect logic. The RIU clock must

be connected in for the BISC process to complete. (ctrl_clk Is used for clocking RIU in Versal devices).

riu_addr Input Register Address.
riu_wr_data[15:0] Input Data write to register.
riu_rd_data[15:0] Output Data read form register.
riu_valid Output Asserts when the user has control over the RIU bus.
riu_wr_en Input Active high register write enable.
riu_nibble_sel Input

Nibble in byte select. This signal must be High to

perform read/write to the nibble.