SGMII LVDS Clocking Logic - 16.2 English - PG047

The SGMII LVDS solution is a synchronous implementation where an external clock is provided to the design. In the example design this clock is assumed to be a 125 MHz differential clock. Clocking logic is similar to7 series implementation.

The differences in clocking logic compared to 7 series implementation follow:

• Internal clocks generated by the MMCM, Clk208 and Clk104 are not required by the UltraScale device implementation of SGMII over LVDS design.
• An additional clock Clk312 (312.5 MHz) generated internally by the MMCM is required by the UltraScale device implementation of SGMII over LVDS design.